This invention relates to an integrated circuit (IC) mounting a non-volatile semiconductor memory such as a flash memory, as well as an IC having a CPU also mounted thereon. In particular, the invention relates to the technology of making use of the results of a burn-in test on such an IC for its later use.
FIG. 4 shows a conventional non-volatile semiconductor memory IC 10 of a simple structure, mounting a non-volatile semiconductor memory serving as a flash memory 11. Many memory cells which can be electrically erased and rewritten simultaneously are arranged in arrays in the flash memory 11, and an access circuit 12 comprising address decoders and sense amplifiers is attached to it. If a control signal for a read or write operation with an address signal A is received by the access circuit 12 from outside through a terminal 13, the corresponding address in the flash memory 11 is accessed and an operation such as the output of a data signal D is carried out.
FIG. 5 shows another conventional IC 20 having not only a flash memory 11 (a non-volatile semiconductor memory) but also a CPU 21 mounted on one chip. This IC 20 includes a bus line 22 for connecting the CPU 21 with the flash memory 11 such that the CPU 21 can access the flash memory 11 therethrough. A ROM 23 for storing application programs and a DRAM 24 for carrying out operations may be also included and connected to the bus line 22, depending on the nature of the application. Also included is a logic circuit 25 for switching the access to the flash memory 11 selectively either through the CPU 21 or directly through terminals 13. If signals such as a mode signal M or a reset signal R are inputted from outside to the logic circuit 25 through terminals 26, suitable selection-switching signals S1 and S2 are generated according to the mode specified at the time of a reset. In a normal mode, the CPU 21 will be caused to access the flash memory 11 through the bus line 22 in response to selection-switching signal S1. In a test mode in view, for example, of a burn-in test, on the other hand, the access circuit 12 will serve to switch the connection of the flash memory 11, separating the flash memory 11 from the bus line 22 and connecting it to the terminals 13. Thus, as is the case with the IC 10 described above with reference to FIG. 4, a direct external access to the flash memory 11 through the terminals 13 becomes effective in such a test mode.
Japanese Patent Publication Tokkai 9-219099 disclosed still another IC which is functionally somewhere between the ICs 10 and 20 described above, being characterized as comprising a so-called self burn-in circuit, instead of a CPU, together with a flash memory for carrying out a burn-in test. In addition to the functions of the IC 10 of FIG. 4, this IC is adapted to carry out a test such as a burn-in test even in the absence of a signal input indicative of a test mode and to transmit the test results to a tester.
Either all or selected ones of such prior art non-volatile semiconductor memory ICs are subjected to a burn-in test. Such a burn-in test which has been carried out conventionally is schematically shown in FIG. 6. Since it is desirable to increase the yield of products, and since it is possible, even if a tested IC is found to have defective portions in its flash memory, to exclude such defective portions from being accessed and to treat the IC as a non-defective product so long as its total memory capacity is greater than a specified minimum required, the test includes not only a usual burn-in test process but also a subsequent process of writing necessary access data (herein referred to as the "status") into the tested non-volatile semiconductor memory IC.
To start the subject IC 10 (or 20, for example) is set inside a heater 30 for a cycle test and a burn-in test with the use of a tester 40 connected to the heater 30 through cables 31. Since it is the tester 40 that controls the tests, it is the tester 40 that sets the temperature of the heater 30 and accesses the IC 10, writing and reading data thereinto and therefrom. The results of the tests and the access data obtained by determining good or bad on the basis of obtained test results are outputted, that is, displayed on a display device 41 or a printed out by a printer 42 which may both be attached to the tester 40.
After the burn-in test is finished, the IC 10 is removed from the heater 30 and is set to a ROM writer 50 for the subsequent write process. Portions corresponding to the IC 10 are extracted from this output obtained, say, through the printer 42, and a map 11a is generated either directly from the portion of the data showing defective parts of the flash memory 11 or after converting such data into a more easily readable format including flag bits and an address list for indicating the addresses of substitute areas. Thereafter, the map 11a thus prepared is written on an available area of the flash memory 11. This process may be carried out by operating the ROM writer 50 while referencing the output data, say, from the printer 42.
When use is made of an IC 10 having such a map 11a written in its flash memory 11, the map 11a serves to prevent data from being written in or read from any of the defective portions of the flash memory 11. In summary, the results of the burn-in test are reflected in a later process such that even the IC products found to have defective portions in their flash memory can be treated as usable products.
According to this prior art technology, however, the burn-in test process which is carried out by accessing a non-volatile semiconductor memory and the subsequent write process whereby access data based on the test results are written in were separate processes each requiring human efforts. When a large number of ICs are to be processed, the operation of the ROM writer 50, for example, is enormously time-consuming. Moreover, it involves a cumbersome work to correctly associate the outputted access data with the individual ICs. Since non-volatile semiconductor memories with different memory capacities and structures are required for different applications, furthermore, the tester has to be modified in various ways in order to accommodate all these different kinds of memories.
It now goes without saying that the number of steps should be reduced as much as possible in the process for the testing. In addition, it is desirable to arrange these steps such that they can be performed continuously and automatically and that some apparatus can be used for different purposes or dispensed with. Although it may be said that the IC described in aforementioned Japanese Patent Publication Tokkai 9-219099 has contributed in improving the efficiency in the use of a tester because it contains within itself a self burn-in circuit, the improvement is only in reducing the number of control signals exchanged with the tester during a burn-in test such that a large number of chips can be tested at the same time. The problem of the amount of work to be done by the operator and the adaptability of the tester to a wide variety of ICs has not been considered.